1. Field of the Invention
The present invention generally relates to packet switches. More specifically, the invention relates to apparatus and methods for buffering packets by implementing a central memory buffered packet switch.
2. Description of Related Art
A packet switch is often used to facilitate delivery of packets in a system (e.g., telecommunication, networking, programmable device, etc.). The packet switch is operable to channel incoming data from one of multiple input ports to a specific output port, which will route the data towards its intended destination.
Packet switches are available in different configurations. One configuration uses an input buffering technique, which allows head of line packets contending for the same output port to reside in respective input buffers where they can be routed one at a time to the output buffer. Although input buffering controls the problem of contention, head of line blocking may occur. That is, these head of line packets may block other packets behind them while waiting for their turn to be routed to the output buffer. This is of concern when other packets in the back of the line are destined for output ports that are readily available for receiving them. In order to mitigate head of line blocking, another configuration includes an output buffering technique. However, this technique requires faster internal switching. It may also produce “backpressure” on specific input ports when a single output buffer is full. Still another configuration employs a central buffering memory to increase internal switching efficiency. Although this technique can work well, to date it has been limited to processing packets according to specific protocols, fixed lengths, custom application-specific integrated circuit (ASIC) designs, or application-specific standard product (ASSP) designs. In addition, configurability for high packet throughput is difficult.
In view of the foregoing, an improved packet switching technique and apparatus would be highly beneficial.